Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-09-23
2000-03-14
Baker, Stephen M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714773, G06F 1110, G11C 2900
Patent
active
060386932
ABSTRACT:
A multi-way, set-associative cache utilizes a single ECC code in which the ECC bits are evenly distributed among the tag arrays to protect all of the multi-way tags. The cache includes a plurality of data arrays--one for each way of the cache--along with a corresponding plurality of tag arrays. The ECC bits are appended to each tag entry for one of the multiple ways. A single ECC logic block is shared by the tag arrays to detect tag errors. Additional comparator logic is coupled to the tag arrays to perform tag matching.
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Baker Stephen M.
Intel Corporation
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