System for assigning a received data packet to a data communicat

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation

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710 5, 710 22, 379 59, 34082551, 455434, G06F 1300, G06F 1314

Patent

active

059480807

ABSTRACT:
DMA channel receive packet comparator logic (74) of PCI-interface ASIC (20) assigns a data packet (106) through a data communications channel and includes DMA channel comparator logic (110) for receiving at least a portion of an incoming data packet (108) in data comparison circuit (110). Data packet comparison circuit (120) compares at least a portion of incoming data packet (108) to a predetermined match data set (122). Packet portion (108) and the match data set (122) form programmably varying data fields (WD0, WD1) corresponding to at least one data communications channel (117, 119,121, 123). In the event of a predetermined correspondence between portion (108) and match data set (122), a channel select signal (117, 119, 121, 123) goes to a channel priority encoder (125).

REFERENCES:
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patent: 5160923 (1992-11-01), Sugawara et al.
patent: 5606561 (1997-02-01), Scheibel, Jr. et al.
patent: 5675732 (1997-10-01), Majeti et al.
patent: 5701302 (1997-12-01), Geiger
patent: 5752076 (1998-05-01), Munson
patent: 5768267 (1998-06-01), Raith et al.

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