Method for the automatic address generation of modules within cl

Details Method for the automatic address generation of modules within cl Method for the automatic address generation of modules within cl

1997-10-08

2000-03-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

711217, 711218, 711220, G06F 938

Patent

active

060386509

ABSTRACT:
A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address the individual elements directly for reconfiguration. This is a prerequisite for being able to reconfigure parts of the unit by an external primary logic unit without having to change the entire configuration of the unit. In addition, the addresses for the individual elements of the units are automatically generated in the X and Y directions, so that the addressing scheme represents the actual arrangement of units and configurable elements. Furthermore, manual allocation of addresses is not necessary due to automatic address generation. In accordance with the present invention, a cluster is provided with a number of configurable units, each having two inputs for receiving the X address of the last element of the preceding unit in the X direction (row) and the Y address of the last element of the preceding unit in the Y direction (column) and having two outputs to relay to the next unit the position of the last element of the unit in the X direction and in the Y direction.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4706216 (1987-11-01), Carter
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4761755 (1988-08-01), Ardini et al.
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4901268 (1990-02-01), Judd
patent: 4967340 (1990-10-01), Dawes
patent: 5014193 (1991-05-01), Garner et al.
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 5021947 (1991-06-01), Campbell et al.
patent: 5023775 (1991-06-01), Poret
patent: 5081375 (1992-01-01), Pickett et al.
patent: 5109503 (1992-04-01), Cruickshank et al.
patent: 5123109 (1992-06-01), Hillis
patent: 5125801 (1992-06-01), Nabity et al.
patent: 5128559 (1992-07-01), Steele
patent: 5142469 (1992-08-01), Weisenborn
patent: 5204935 (1993-04-01), Mihara et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5226122 (1993-07-01), Thayer et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5247689 (1993-09-01), Ewert
patent: 5287472 (1994-02-01), Horst
patent: 5301344 (1994-04-01), Kolchinsky
patent: 5303172 (1994-04-01), Magar et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5418952 (1995-05-01), Morley et al.
patent: 5421019 (1995-05-01), Holsztynski et al.
patent: 5422823 (1995-06-01), Agrawal et al.
patent: 5426378 (1995-06-01), Ong
patent: 5430687 (1995-07-01), Hung et al.
patent: 5440245 (1995-08-01), Galbraith et al.
patent: 5442790 (1995-08-01), Nosenchuck
patent: 5444394 (1995-08-01), Watson et al.
patent: 5448186 (1995-09-01), Kawata
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457644 (1995-10-01), McCollum
patent: 5473266 (1995-12-01), Ahanin et al.
patent: 5473267 (1995-12-01), Stansfield
patent: 5475583 (1995-12-01), Bock et al.
patent: 5475803 (1995-12-01), Stearns et al.
patent: 5483620 (1996-01-01), Pechanek et al.
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5485104 (1996-01-01), Agrawal et al.
patent: 5489857 (1996-02-01), Agrawal et al.
patent: 5491353 (1996-02-01), Kean
patent: 5493239 (1996-02-01), Zlotnick
patent: 5497498 (1996-03-01), Taylor
patent: 5506998 (1996-04-01), Kato et al.
patent: 5510730 (1996-04-01), El Gamal et al.
patent: 5511173 (1996-04-01), Yamaura et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5532693 (1996-07-01), Winters et al.
patent: 5532957 (1996-07-01), Malhi
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5537057 (1996-07-01), Leong et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5541530 (1996-07-01), Cliff et al.
patent: 5544336 (1996-08-01), Kato et al.
patent: 5548773 (1996-08-01), Kemney et al.
patent: 5555434 (1996-09-01), Carlstedt
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5561738 (1996-10-01), Kinerk et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5586044 (1996-12-01), Agrawal et al.
patent: 5587921 (1996-12-01), Agrawal et al.
patent: 5588152 (1996-12-01), Dapp et al.
patent: 5590345 (1996-12-01), Barker et al.
patent: 5590351 (1996-12-01), Sowadsky et al.
patent: 5708842 (1998-01-01), Ikegaya et al.
patent: 5822608 (1998-10-01), Dieffenderfer et al.
patent: 5842034 (1998-11-01), Bolstad et al.
Villasenor, John, et al., "Configurable Computing." Scientific American, vol. 276, No. 6, Jun. 1997, pp. 66-71.
Villasenor, John, et al., "Configurable Computing Solutions for Automatic Target Recognition," IEEE, 1996 pp. 70-79.
Tau, Edward, et al., "A First Generation DPGA Implementation," FPD'95, pp. 138-143.
Athanas, Peter, et al., "IEEE Symposium on FPGAs For Custom Computing Machines," IEEE Computer Society Press, Apr. 19-21, 1995, pp. i-vii, 1-222.
Bittner, Ray, A., Jr., "Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System," Dissertation, Jan. 23, 1997, pp. i-xx, 1-415.
Myers, G., Advances in Computer Architecture, Wiley-Interscience Publication, 2nd ed., John Wiley & Sons, Inc. pp. 463-494, 1978.
M. Saleeba, "A Self-Contained Dynamically Reconfigurable Processor Architecture", Sixteenth Australian Computer Science Conference, ASCS-16, QLD, Australia, Feb., 1993.
M. Morris Mano, "Digital Design," by Prentice Hall, Inc., Englewood Cliffs, New Jersey 07632, 1984, pp. 119-125, 154-161.
Maxfield, C. "Logic that Mutates While-U-Wait" EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA .

Affiliated with

Also associated with

Rating

Method for the automatic address generation of modules within cl does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for the automatic address generation of modules within cl, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the automatic address generation of modules within cl will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-179776