Semiconductor memory device having the same access timing over c

Details Semiconductor memory device having the same access timing over c Semiconductor memory device having the same access timing over c

1996-09-04

2000-03-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

711104, 711219, G11C 11401

Patent

active

060386487

ABSTRACT:
In order to generate internal addresses from an external address in a burst operation in a synchronous dynamic random access memory (SDRAM), an external address is latched in response to an external clock signal. First and second control signals are generated in synchronous with the external clock signal. An internal address for a first clock cycle of a burst operation is generated from the latched external address in a sequential mode in response to the first control signal using a first transfer path. An internal address for each of a second clock cycle and subsequent clock cycles of the burst operation in the sequential mode is generated in response to a second control signal using a second transfer path such that the internal address for each of the second clock cycle and subsequent clock cycles has substantially the same delay time as that of the internal address for the first clock cycle with respect to the external clock signal. The first control signal is generated based on a command signal for designating a read or write operation, in response to an internal clock signal synchronous with the external clock signal and the second control signal is generated in the burst operation in response to the internal clock signal.

REFERENCES:
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patent: 5347232 (1994-09-01), Nishimichi
patent: 5426606 (1995-06-01), Takai
patent: 5550784 (1996-08-01), Takai
patent: 5608686 (1997-03-01), Takai
patent: 5610874 (1997-03-01), Park et al.
patent: 5634030 (1997-05-01), Nakano

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