Method of and apparatus for speeding up the execution of normal

Details Method of and apparatus for speeding up the execution of normal Method of and apparatus for speeding up the execution of normal

1998-02-20

2000-06-27

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

711 2, G06F 1200

Patent

active

060818816

ABSTRACT:
A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and one memory bank in an extended mode. This invention provides fast transfer hardware to improve the response time by a speed up transfer for normal extended mode transfer instructions only. The bank descriptor of the instruction is used to determine appropriate transfer instructions which are then tested for characteristics indicating whether a fast transfer is possible. The fast transfer process requires fewer checks than the previous apparatus which accelerates the response to selected transfer instructions by one cycle.

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