Method for transferring burst data in a microprocessor

Details Method for transferring burst data in a microprocessor Method for transferring burst data in a microprocessor

1998-03-03

2000-06-27

Nguyen, Hiep T

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

710 34, 711118, 711137, 711213, 711217, 711218, 711219, 711220, 36523003, 365236, 365239, G06F 1206

Patent

active

060818530

ABSTRACT:
A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

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1997 IEEE International Solid State Circuits Conference, ISSCC97/Non-Volatile Memory and SRAM/Paper SP24.6.

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