Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1976-08-17
1979-01-09
Konick, Bernard
Static information storage and retrieval
Read/write circuit
Data refresh
365154, G11C 700, G11C 1140
Patent
active
041341503
ABSTRACT:
Memory cells in a random access memory system are addressed through associated X and Y address lines. Each memory cell is operable as a static memory device to represent "1" binary data in response to a first control potential applied to the associated X address line and a first data input potential applied to the associated Y address line and further operable as a nonstatic memory device to represent "0" binary data in response to the first control potential applied to the X address line and to a second data input potential applied to the Y address line. Means are provided to refresh the stored "0" binary data by simultaneously applying a second control potential lower than the first control potential to all of the X address lines at periodic intervals and simultaneously therewith applying the second data input potential to all of the Y address lines.
REFERENCES:
patent: 3618053 (1971-11-01), Hudson et al.
patent: 3644907 (1972-02-01), Gricchi et al.
patent: 3858185 (1974-12-01), Reed
patent: 3968479 (1976-07-01), Goser
patent: 3997881 (1976-12-01), Hoffman
Konick Bernard
Matsushita Electric - Industrial Co., Ltd.
McElheny Donald
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