SRAM semiconductor device

Static information storage and retrieval – Systems using particular element – Flip-flop

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365156, 257536, 257537, 257904, G11C 1100

Patent

active

055703119

ABSTRACT:
An SRAM semiconductor device having a parallel connection of two series circuits each having a driver transistor and a load connected in series, a wiring for connecting an interconnection point between the driver transistor and load of each of the two series circuits to a control terminal of the driver transistor of the other of the two series circuits, and a transfer transistor connected to each interconnection point, wherein the driver transistor and transfer transistor each are an insulating gate field effect transistor having a channel region formed on the surface of a semiconductor substrate at a predetermined area, source/drain regions on both sides of the channel region, and an insulated gate above the channel region, and the transfer transistor has a resistor region having an impurity concentration lower than the source/drain regions on both sides of the channel region of the driver transistor, the resistor region being contiguous to the channel region of the transfer transistor.

REFERENCES:
patent: 4995000 (1991-02-01), Terrell
patent: 5172211 (1992-12-01), Godinho et al.
patent: 5239196 (1993-08-01), Ikeda et al.
patent: 5377140 (1994-12-01), Usuki
Ohkubo et al., 16M bit SRAM Cell Technologies for 2.0V Operation, IEDM Technical Digest 1991, pp. 481-484.

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