Dynamic semiconductor memory device having high integration dens

Details Dynamic semiconductor memory device having high integration dens Dynamic semiconductor memory device having high integration dens

1992-07-01

1994-11-08

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

365177, 257273, 257360, 257363, 257370, G11L 1124

Patent

active

053633253

ABSTRACT:
A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

REFERENCES:
patent: 4677589 (1987-06-01), Haskell et al.
patent: 4961165 (1990-10-01), Ema
patent: 5031020 (1991-07-01), Momose
patent: 5198995 (1993-03-01), Dennard et al.
"A Block Oriented RAM with Half-Sized DRAM Cell and Quasi-folded Data Line Architecture", Kimura et al ISSCC91/Session 6/High Density DRAM/Paper TA 6.2, Mar. 1991 IEEE.
"Cell Plate Line Connecting Complementary Bitline (C.sup.3) Architecture For Battery Operating DRAMs", Asakura et al., LSI Research and Development Lab, Mitsubishi Electric Corporation.
Technical Digest of IEDM, "A Bipolar-EPROM (Bi-EPROM) Structure for 33 v Operation and High Speed Application" N. Matsukawa, et al., 1990, pp. 90-313-90-316.

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