Flash memory cell with self-aligned tunnel dielectric area above

Details Flash memory cell with self-aligned tunnel dielectric area above Flash memory cell with self-aligned tunnel dielectric area above

1995-05-05

1996-10-29

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257317, 257319, 257321, 36518526, 36518516, 36518528, 36518533, H01L 2976, H01L 29788, G11C 1134

Patent

active

055699464

ABSTRACT:
This invention provides a stacked gate flash memory cell structure and a method for forming the stacked gate flash memory structure. The invention uses a large angle ion implant beam without wafer rotation to form the source and drain regions of the memory cell. A low doped region is formed between an edge of the first gate electrode and an edge of either the source or drain regions. The tunnel dielectric is formed directly above the low doped region. The width of the low doped region is controlled by the angle of the large angle ion implant beam and can be very accurately controlled. The tunnel dielectric is formed independently of the gate dielectric and the thickness of each can be optimized. The tunnel dielectric area can be made very small which improves reliability and reduces the voltage necessary to program and erase the memory cell.

REFERENCES:
patent: 5223451 (1993-06-01), Uemura et al.
patent: 5482879 (1996-01-01), Hong
patent: 5486714 (1996-01-01), Hong
patent: 5502321 (1996-03-01), Matsushita
patent: 5504358 (1996-04-01), Hong
Hisamune et al., "A High Capacitive-Coupling Ratio (HiCR) Cell for 3V-Only 64 Mbit and Future Flash Memories", IEEE-IEDM, Dec. 1993, pp. 19-22.

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