Device and method to reduce power consumption in integrated semi

Details Device and method to reduce power consumption in integrated semi Device and method to reduce power consumption in integrated semi

1998-05-07

2000-06-27

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 93, 326 95, 326 98, 326 94, 326 30, 326119, 326121, 327227, 327407, 327408, H03K 1900, H03K 3033

Patent

active

060811358

ABSTRACT:
According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

REFERENCES:
patent: 5384493 (1995-01-01), Furuki
patent: 5440243 (1995-08-01), Lyon
patent: 5557620 (1996-09-01), Miller, Jr. et al.
patent: 5841300 (1998-11-01), Murabayashi et al.

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