Method for protecting an ASIC by resetting it after a predetermi

Details Method for protecting an ASIC by resetting it after a predetermi Method for protecting an ASIC by resetting it after a predetermi

1994-06-30

1996-07-16

Hudspeth, David R.

Electronic digital logic circuitry

Security

326 16, 326 93, 380 4, 327142, H04L 900

Patent

active

055370551

ABSTRACT:
A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

REFERENCES:
patent: 4609777 (1986-09-01), Cargile
patent: 4970418 (1990-11-01), Masterson
patent: 5343085 (1994-08-01), Fujimoro et al.
patent: 5359233 (1994-10-01), Mumper et al.

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