MOS semiconductor device with self-aligned punchthrough stops an

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257344, 257408, H01L 2976, H01L 2994, H01L 31062

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active

060810106

ABSTRACT:
A novel high-speed, highly reliable VLSI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode. A first source region and a first drain region of a first concentration dopant of a second conductivity type are disposed in the first and the second punchthrough stop regions, respectively, self-aligned with the outer edges of the conductive spacers.

REFERENCES:
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patent: 5091763 (1992-02-01), Sanchez
patent: 5218221 (1993-06-01), Okumura
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