VLSIC semiconductor memory device with cross-coupled inverters w

Details VLSIC semiconductor memory device with cross-coupled inverters w VLSIC semiconductor memory device with cross-coupled inverters w

1994-12-22

1996-07-16

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257297, 257903, 365154, 365156, 365190, G11C 1100, G11C 700, H01L 2711

Patent

active

055369600

ABSTRACT:
A static random access memory (SRAM) has a plurality of static memory cells each of which has a set of cross coupled inverters having first and second inverters. The first inverter has first and second transistors. The second inverter has primary and secondary transistors. Each of the first and the primary transistors may be, for example, a P-channel transistor. Each of the second and the secondary transistors may be, for example, an N-channel transistor. The static memory cell further has a first diode having a first forward direction and a second diode having a second forward direction. The first forward direction is directed from drains of the primary and secondary transistors to a gate of the first transistor. The second forward direction is directed from drains of the first and the second transistors to a gate of the primary transistor.

REFERENCES:
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
"Improvement of Soft Error Immunity in a Polysilicon PMOS Load Memory Cell" by Ueda et al., published on Autumnal Conference of the Institute of Electronics, Information, and Communication Engineers in 1991, pp. 5-141.

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