Method a CMOS transistor and isolated back electrodes on an SOI

Details Method a CMOS transistor and isolated back electrodes on an SOI Method a CMOS transistor and isolated back electrodes on an SOI

1996-10-03

2000-06-27

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438154, 438283, H01L 2184

Patent

active

060806109

ABSTRACT:
The present invention is intended to provide, in MOS transistors used as a bonding layer for silicon regions of an SOI substrate, an nMOS transistor on a silicon region of an SOI substrate which uses a polycrystalline silicon layer as a layer to be bonded with the silicon substrate and a pMOS transistor on another silicon region of the SOI substrate and electrically isolated back gate electrodes through a back gate insulation film on the silicon region side between the silicon regions and a polycrystalline silicon layer. A leak current is reduced and a malfunction of the transistors is eliminated by providing pickup electrodes for the back gate electrodes.

REFERENCES:
patent: 4980308 (1990-12-01), Hayashi et al.
patent: 4996575 (1991-02-01), Ipri et al.
patent: 5185535 (1993-02-01), Farb et al.
patent: 5202273 (1993-04-01), Nakamura
patent: 5399509 (1995-03-01), Iranmanesh
patent: 5437762 (1995-08-01), Ochiai et al.
patent: 5474952 (1995-12-01), Fujii
patent: 5597739 (1997-01-01), Sumi et al.

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