Memory in which improvement is made as regards a precharge opera

Details Memory in which improvement is made as regards a precharge opera Memory in which improvement is made as regards a precharge opera

1994-08-26

1995-10-31

Nelms, David C.

Static information storage and retrieval

Read/write circuit

365191, 365233, 365203, G11C 700

Patent

active

054635810

ABSTRACT:
In a semiconductor memory device having first and second main data amplifiers (27, 28) for electrically charging a plurality of read bus pairs (23, 24), a precharge control circuit (26) controls operation of first and second main data amplifiers so that selected ones of the read bus pairs are electrically charged during a predetermined burst period except when each of the first and the second main data amplifiers produces a difference signal. When each of the read bus pairs has a read bus potential difference, each of the first and the second main data amplifiers produces the difference signal and electrically charges each of the read bus pairs in accordance with the difference signal. The read bus potential difference is produced dependent on a bit line potential difference which is produced in each of bit line pairs.

REFERENCES:
patent: 5268865 (1993-12-01), Takasugi
patent: 5291447 (1994-03-01), Kodama
patent: 5371715 (1994-12-01), Kim

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