Technique for accelerating instruction decoding of instruction s

Details Technique for accelerating instruction decoding of instruction s Technique for accelerating instruction decoding of instruction s

1994-07-15

1997-01-07

Harvey, Jack B.

395389, G06F 930

Patent

active

055926355

ABSTRACT:
In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions concurrently while they are being fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.

REFERENCES:
patent: 3656123 (1972-04-01), Carnvale et al.
patent: 3657705 (1972-04-01), Mekota et al.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4236206 (1980-11-01), Strecker et al.
patent: 4325118 (1982-04-01), DeVita et al.
patent: 4346437 (1982-08-01), Blahut et al.
patent: 4363091 (1982-12-01), Pohlman, III et al.
patent: 4454578 (1984-06-01), Matsumoto
patent: 4502111 (1985-02-01), Riffle et al.
patent: 4890218 (1989-12-01), Bram
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5117488 (1992-05-01), Noguchi et al.
Lindauer et al., Instruction Unit, IBM Technical Disclosure Bulletin, vol. 7, No. 1, Jun. 1964.

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