Dual-port static random access memory cell

Details Dual-port static random access memory cell Dual-port static random access memory cell

1991-04-24

1994-02-22

Pascal, Robert J.

Static information storage and retrieval

Addressing

Multiple port access

36518909, 36518911, 365228, G11C 800

Patent

active

052894320

ABSTRACT:
A dual port SRAM is shown which comprises first and second word lines and first and second bit lines. A pair of semiconductor memory devices are cross coupled into a bistable circuit for storing true and complement logic levels and are coupled between common and power supply lines. A first access semiconductor is connected between the first bit line and one semiconductor memory device, and its control electrode is connected to the first word line. A second access semiconductor is connected between the second bit line and another of the semiconductor memory devices, and its control electrode is connected to the second word line. A write circuit is provided for applying write potentials to the first bit and word lines to switch the conduction states of the semiconductor memory devices. A further circuit is provided for reducing the voltage level on the power supply line when the write circuit applies the write potentials, the voltage reduction not being greater than 50% of its prereduction level, so that the potential at the second access semiconductor still exhibits a proper logic level in accordance with the memory state of the cell.

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Kevin J. O'Connor, The Twin-Port Memory Cell, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5 Oct. 1987, pp. 712-720.

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