Semiconductor memory device having a capability for controlled a

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36523003, G11C 1300

Patent

active

055924336

ABSTRACT:
A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.

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