Method and apparatus for performing TLB shutdown operations in a

Details Method and apparatus for performing TLB shutdown operations in a Method and apparatus for performing TLB shutdown operations in a

1996-12-19

1999-05-18

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711141, G06F13/14

Patent

active

059060018

ABSTRACT:
Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown operation of the present invention provides for a TLB flush transaction communicated between multiple processors on a host bus. One microprocessor issues a TLB flush request on the host bus. The TLB flush request includes a page number. The microprocessors receiving the request invalidate the TLB entry corresponding to the page number.

REFERENCES:
patent: 5317705 (1994-05-01), Gannon
patent: 5497480 (1996-03-01), Hayes et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5555420 (1996-09-01), Sarangdhar et al.
patent: 5574878 (1996-11-01), Onodera
patent: 5574936 (1996-11-01), Ryba

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