Computer with a cache controller and cache memory with a priorit

Details Computer with a cache controller and cache memory with a priorit Computer with a cache controller and cache memory with a priorit

1997-02-18

1999-05-18

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711158, 711133, 711159, G06F12/00

Patent

active

059060000

ABSTRACT:
A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.

REFERENCES:
patent: 4490782 (1984-12-01), Dixon et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5651135 (1997-07-01), Hatakeyama

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