Combined cache tag and data memory architecture

Details Combined cache tag and data memory architecture Combined cache tag and data memory architecture

1996-07-29

1999-05-18

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, 711129, 711 5, 365 51, 365205, G06F12/08

Patent

active

059059966

ABSTRACT:
A cache memory circuit for use in a cache memory system having a predetermined width is comprised of a memory array divided into a cache data memory portion and a tag memory portion. The proportion of the tag memory portion with respect to the cache data memory portion is the same as the proportion of the cache data memory portion to the width of the cache memory system. Support circuitry is provided for reading information into and out of both of the memory portions. A method for laying out such a cache memory circuit is also disclosed.

REFERENCES:
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5353424 (1994-10-01), Partovi et al.
patent: 5564034 (1996-10-01), Miyake

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