Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

1995-06-06

1997-01-07

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257903, 257904, H01L 2976

Patent

active

055920136

ABSTRACT:
In a semiconductor memory device, an n-well is formed in the memory cell area on the surface of a p-type semiconductor substrate. A p-well is formed on the surface of the n-well, and a memory cell transistor is formed on the surface of the p-well. Another p-well is formed in the peripheral circuit area on the substrate surface, and a peripheral transistor is formed on the surface of the p-well. The p-wells are connected electrically by a conductor layer so that these regions have the same voltage level. The memory cell transistor has its threshold voltage set higher than that of the peripheral transistor. The memory device consumes less power, has less decay of gate oxide film, and is suitable for high-density integration.

REFERENCES:
patent: 4472871 (1984-09-01), Green et al.
patent: 4525811 (1985-06-01), Masuoka
patent: 5020029 (1991-05-01), Ichinose et al.
patent: 5455438 (1995-10-01), Hashimoto et al.
Evert Seevinck et al., Static-Noise Margin Analysis of MOS SRAM Cells, pp. 748-754, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.
H. Shinohara et al, Parasitic Resistance Effects on Static MOS RAM, pp. 106 and 107, VLSI 1982.

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