Single layer thin film transistor static random access memory ce

Details Single layer thin film transistor static random access memory ce Single layer thin film transistor static random access memory ce

1995-06-23

1997-01-07

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257930, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

055920110

ABSTRACT:
A memory cell layout and method of forming a 6 transistor SRAM memory cell that achieves a reduced cell area using uncomplicated fabrication steps. In one embodiment, a six transistor (6/T) SRAM cell has two horizontal thin-film transistor (T5, T6) as load transistors, two transfer transistors (T1, T2), two latch transistors (T3, T4) and two current nodes (38, 40). In this structure all six transistors are formed in the substrate and a single polysilicon layer.

REFERENCES:
patent: 5198683 (1993-03-01), Sivan
patent: 5350933 (1994-09-01), Yoshihara

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