Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1996-04-05

1997-01-07

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257321, 36518505, 36518526, H01L 29788

Patent

active

055920012

ABSTRACT:
There is disclosed a non-volatile semiconductor memory device wherein a pair of memory cells constituting one bit data memory unit are connected to a data line in a manner that their drains are commonly connected. When compared to the case where drains of two memory cells are respectively connected to different data lines, the number of the connecting portions between drains and data lines is reduced and the area required for connection is lessened. Thus, a semiconductor memory device satisfactorily miniaturized from the viewpoint of practical use is provided. Further, since there is employed an arrangement such that the one bit data memory unit is comprised of two (a pair of) memory cells, the reliability can be improved. Individual select transistors may be arranged between the drain common junctions in the pair of memory cells, respectively, or a common select transistor may be arranged therebetween. In addition, the sources of the two memory cells may be respectively formed as individual sources.

REFERENCES:
patent: 4462090 (1984-07-01), Iizuka
patent: 4807188 (1989-02-01), Casagrande
patent: 4967393 (1990-10-01), Yokoyama et al.
patent: 5034798 (1991-07-01), Ohsima
Cioaca et al., "A Million-cycle CMOS 256K EEPROM", Digest of Technical Papers, p. 78, 1987. IEEE Int. Sol. St. Cir. Conf.
Ali et al., "A 50-ns 256K CMOS Split-Gate EPROM", IEEE Journal of Soid State Circuits, vol. 23, No. 1, Feb. 1988, New York, pp. 79-85.

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