Read circuit for large-scale dynamic random access memory

Details Read circuit for large-scale dynamic random access memory Read circuit for large-scale dynamic random access memory

1990-11-26

1993-07-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

365190, 36523006, G11C 700

Patent

active

052299643

ABSTRACT:
A circuit for reading and writing data to/from memory cells of a DRAM, based upon sense amplifiers formed of N-type and P-type FETs for each pair of bit lines of the DRAM and column switches formed of FETs for transferring data potentials to/from the bit line pairs, in which the current drive capability of the column switches is increased relative to the sense amplifiers during each write cycle and the current drive capability of the sense amplifiers is increased relative to that of the column switches during each read cycle, thereby ensuring satisfactory read and write operation even for a very large-scale DRAM operating with a low value of supply voltage.

REFERENCES:
patent: 4168539 (1979-09-01), Anderson
patent: 4839868 (1989-06-01), Sato et al.
patent: 4916668 (1990-04-01), Matsui
patent: 5005154 (1991-04-01), Masuda
patent: 5050127 (1991-09-01), Mitsijmoto et al.

Affiliated with

Also associated with

Rating

Read circuit for large-scale dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read circuit for large-scale dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read circuit for large-scale dynamic random access memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1766182