Semiconductor nonvolatile memory device for controlling the pote

Details Semiconductor nonvolatile memory device for controlling the pote Semiconductor nonvolatile memory device for controlling the pote

1991-08-02

1993-07-20

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 36518911, 365226, G11C 1134

Patent

active

052299635

ABSTRACT:
A nonvolatile semiconductor memory device comprising a power source terminal and a P-channel MOS transistor. A low power-source voltage is applied to the terminal during a read period. The source of the P-channel MOS transistor is coupled to the power source terminal. The conduction of the MOS transistor is controlled by data-writing operation. The drain of the MOS transistor is connected by a node to a plurality of bit lines. The device further comprises a plurality of memory cells and a plurality of N-channel MOS transistor. The memory cells have double-gate structure, each having a source coupled to the ground and a drain coupled to the corresponding bit line. Each N-channel MOS transistor has a source and a drain connected to the ground and the corresponding bit line, respectively, for discharging the bit line. Each N-channel MOS transistor is rendered conductive temporarily when the supply of the high power source voltage to the power source terminal is started, whereby the potential of the corresponding bit line is decreased. The bit-line potential is decreased sufficiently since the P-channel MOS transistors have a conductance greater than that of any other transistor incorporated in the device.

REFERENCES:
patent: 4527256 (1985-07-01), Giebel
patent: 5105386 (1992-04-01), Andoh et al.
patent: 5138579 (1992-08-01), Tatsumi et al.

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