Semiconductor memory with separate time-out control for read and

Details Semiconductor memory with separate time-out control for read and Semiconductor memory with separate time-out control for read and

1990-12-14

1993-11-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 700

Patent

active

052589528

ABSTRACT:
A read/write memory having timed-out control of certain of its peripheral circuitry is disclosed. The control circuit for controlling the time at which time-out is to occur includes two delay stages of different lengths. The shorter delay stage is used to define the time-out in a read operation, and the longer delay stage is used to define the time-out in a write operation, since a read operation can generally be accomplished sooner than a write operation. Enabling of the periphery is controlled by an address transition detection circuit, and by a data transition detection circuit. The circuit includes a short path by which enabling of the periphery is performed responsive to a data transition in the absence of an address transition, in order to perform a late write operation.

REFERENCES:
patent: 4580246 (1986-04-01), Sibigtroth
patent: 4916668 (1990-04-01), Matsui
patent: 5031141 (1991-07-01), Guddat
patent: 5031150 (1991-07-01), Ohsawa
patent: 5083296 (1992-01-01), Hara
patent: 5091889 (1992-02-01), Hamano
patent: 5124584 (1992-06-01), McClure
patent: 5124951 (1992-06-01), Slemmer
patent: 5126975 (1992-06-01), Handy
patent: 5128897 (1992-07-01), McClure

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