Method for making electrical contact with an active area through

Fishing – trapping – and vermin destroying

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Details

437 41, 437 44, 437183, 437203, H01L 2144, H01L 2148

Patent

active

052293262

ABSTRACT:
A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first contact opening over the exposed active areas; (i) providing an insulating layer over the nitride layer and the polysilicon plug; (j) patterning and etching the insulating layer to form a second contact opening to and exposing the polysilicon plug; and (k) providing a conductive layer over the insulating layer and into the second opening to electrically contact the polysilicon plug. A semiconductor device having buried landing plugs of approximately uniform height across the wafer is also described.

REFERENCES:
patent: 4617193 (1986-10-01), Wu
patent: 4868138 (1989-09-01), Chan et al.
patent: 4892845 (1990-01-01), Bridges
patent: 5110766 (1992-05-01), Maeda et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5171713 (1992-12-01), Matthews

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