Electrically erasable read only memory cell array having elongat

Details Electrically erasable read only memory cell array having elongat Electrically erasable read only memory cell array having elongat

1992-11-16

1993-11-02

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257331, 365185, H01L 2968, G11C 1134

Patent

active

052586340

ABSTRACT:
An EPROM cell on a semiconductor substrate having a trench containing a source region in the bottom thereof, insulated floating gates on opposite sidewalls of the trench, and a control gate overlying the floating gates. Drain regions are provided beneath the top surface of the substrate, adjacent to the floating gates, which are electrically connected by a conductive stripe on the surface of the substrate that extends transverse to the trench axis.
A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate. An insulated floating gate of polycrystalline silicon is formed on the sidewalls of the trench. Doped regions are formed on the surface of the substrate and in the trench bottom. A control gate is formed over the floating gate. Electrical contact is established to the doped regions and the control gate.

REFERENCES:
patent: 4929988 (1990-05-01), Yoshikawa

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