Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-12-28
1992-06-16
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 2900
Patent
active
051229870
ABSTRACT:
A semiconductor memory device having a redundant circuit includes a substitution memory cell circuit (2) having a spare memory cell, and a switching control circuit (1) for controllably substituting the spare memory cell for an individual defective memory cell whenever the row and column addresses of the defective cell are addressed. The spare memory cell (21) is constituted by a flip-flop and is capable of driving a read data bus (5) without amplification. Hence, it is possible to prevent the delay in accessing from being caused by use of the redundant circuit, as well as preventing excessive density and complexity in the masking pattern for this semiconductor memory. In one aspect of the invention the redundant circuit includes a spare memory cell that has inverters for amplification.
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Hecker Stuart N.
Lane Jack A.
Mitsubishi Denki & Kabushiki Kaisha
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