Semiconductor memory device having burn-in mode operation stably

Details Semiconductor memory device having burn-in mode operation stably Semiconductor memory device having burn-in mode operation stably

1999-04-08

2000-03-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36523003, 36523006, G11C 700

Patent

active

060381833

ABSTRACT:
Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

REFERENCES:
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patent: 5654925 (1997-08-01), Koh et al.
patent: 5673228 (1997-09-01), Timm et al.
patent: 5689467 (1997-11-01), Hashimoto
patent: 5694364 (1997-12-01), Morishita et al.
"A 256 DRAM with Simplified Register Control for Low Power Self Refresh and Rapid Burn-in", S. Yoo et al., 1994 Symposium on VLSI Circuits Digest of Technical papers, pp. 85-86.
"Wafer Burn-in (WBI) Technology for RAM's", T. Furuyama et al., 1993 IEEE, pp. 26.5.1-26.5.4.

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