Dynamic priority switching of load and store buffers in supersca

Details Dynamic priority switching of load and store buffers in supersca Dynamic priority switching of load and store buffers in supersca

1996-04-30

1999-05-18

Lim, Krisna

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

712 23, 710 53, 711158, G06F13/00

Patent

active

059047321

ABSTRACT:
A method and apparatus for dynamically switching the relative priorities of the load buffer and store buffer with respect to external memory resources in a superscalar processor. According to a first embodiment, a protocol dictates that the load buffer always prevails until the store buffer reaches a certain "high water mark," (an upper threshold) at which time the store buffer gains priority. After the store buffer has gained priority, it continues to access the memory until it is depleted to a "low water mark," (a lower threshold) at which time the load buffer regains priority. Whenever the store buffer reaches the high water mark, it gains priority until it drains down to the low water mark. This reduces the tendency for the store buffer to become full and block the processor. According to a second embodiment, the load buffer prevails if it is above its high water mark. If the load buffer is below its high water mark, the load buffer prevails until the store buffer reaches its high water mark, at which time the store buffer gains priority. After the store buffer has gained priority, it maintains priority until the load buffer reaches its high water mark. This reduces the tendency for either buffer to become full and block the processor.

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Tanenbaum; Modern Operating Systems; pp. 56-71, 1992.

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