Method of forming wiring structure

Details Method of forming wiring structure Method of forming wiring structure

1997-10-30

1999-05-18

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438788, 438787, 438629, 438763, 257634, 257635, H01L21/31

Patent

active

059045760

ABSTRACT:
After wiring patterns are formed on an insulating film covering the surface of a substrate, an insulating film such as plasma CVD SiO.sub.2 is formed covering the wiring patterns. A hydrogen silsesquioxane resin film with a flat surface is formed by spin coating or the like on the insulating film. Thereafter, the resin film is changed into a pre-ceramic silicon oxide film by performing heat treatment in an inert gas atmosphere. On this pre-ceramic silicon oxide film, an insulating film such as plasma enhanced CVD SiO.sub.2 film is formed and another wiring layer is formed on the insulating film. This method of forming a multi-layer wiring structure allows an interlayer insulating film to be planarized, and improves a yield of wiring formation.

REFERENCES:
patent: 4756977 (1988-07-01), Haluska et al.
patent: 5059448 (1991-10-01), Chandra et al.
patent: 5085893 (1992-02-01), Weiss et al.
patent: 5118530 (1992-06-01), Hanneman et al.
patent: 5145723 (1992-09-01), Ballance et al.
patent: 5336532 (1994-08-01), Haluska et al.
patent: 5369795 (1994-11-01), Yanagimoto
patent: 5370904 (1994-12-01), Mine et al.
patent: 5380567 (1995-01-01), Haluska
patent: 5399441 (1995-03-01), Bearinger et al.
patent: 5458912 (1995-10-01), Camiletti et al.
patent: 5506177 (1996-04-01), Kishimoto et al.
patent: 5548159 (1996-08-01), Jeng
patent: 5567661 (1996-10-01), Nishio et al.
patent: 5607773 (1997-03-01), Ahlburn et al.
patent: 5683940 (1997-11-01), Yahiro
patent: 5728630 (1998-03-01), Nishimura et al.
patent: 5750403 (1998-05-01), Inoue et al.
Wolf et al., Silicon Process for the VLSI Era, vol. 2, pp. 273-276, 1990.
Patent Abstracts Of Japan, vol. 17, No. 032(E-1309), Jan. 21, 1993 & JP 4-253309, Sep. 9, 1992.
Patent Abstracts Of Japan, vol. 17, No. 075 (E-1320), Feb. 15, 1993 & JP 4-277910, Oct. 2, 1992.
Patent Abstracts Of Japan, vol. 10, No. 283 (E-440), Sep. 26, 1986 & JP 61-101109, May 20, 1986.
B. T. Ahlburn, et al., "A Non-Etch Back Spin on Glass for 0.5.mu.M Devices Using Hydrogen Silsesquioxane As A Replacement For Methylsiloxane", Jun. 7-8, 1994, VMIC Conference, 1994 ISMIC, pp. 120-122.
B.T. Ahlburn, et al., "Hydrogen Silsesquioxane-Based Flowable Oxide as an Element in the Interlevel Dielectric for Sub 0.5 Micron ULSI Circuits", Feb. 21-22, 1995, VMIC Conference, 1995 ISMIC, pp. 36-42.
D.S. Ballance, et al., "Low Temperature Reflow Planarization Using A Novel Spin-On Interlevel Dielectric", Jun. 9-10, 1992, VMIC Conference, 1992 ISMIC, pp. 180-186.
D. Pramanik, et al., "Reliability of Multilevel Circuits Using Hydrogen Silsesquioxane FOx for Interlevel Dielectric Planarization", Jun. 8-9, 1993, VMIC Conference, 1993 ISMIC, pp. 329-331.
Brochure, "Application Notes for Dow Corning Flowable Oxide", 1993, Dow Corning Corporation, pp. 1-4.
R. Dawson, et al., "Performance of Logic Devices Utilizing A Novel Spin-On Dielectric Planarization Process", Jun. 8-9, 1993, VMIC Conference, 1993 ISMIC, p. 218.

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