Simultaneous dielectric planarization and contact hole etching

Details Simultaneous dielectric planarization and contact hole etching Simultaneous dielectric planarization and contact hole etching

1991-11-25

1993-06-29

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156650, 156651, 437228, 437981, 257774, H01L 21302

Patent

active

052230848

ABSTRACT:
During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.

REFERENCES:
patent: 4816115 (1989-03-01), Horner et al.
patent: 4879257 (1989-11-01), Patrick
patent: 4939105 (1990-07-01), Langley
patent: 5026666 (1991-06-01), Hills et al.
patent: 5180689 (1993-01-01), Liu et al.
L. Giffen et al., "Silicon Dioxide Profile Control for Contacts and Vias," Solid State Technology, Apr., 1989, pp. 55-57.

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