Static information storage and retrieval – Read/write circuit – Signals
Patent
1987-11-30
1989-10-17
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Signals
365233, 3652335, G11C 700, G11C 800
Patent
active
048751928
ABSTRACT:
A dynamic semiconductor memory includes a shift register which enables a nibble operation to be carried out, and a timing generator. The timing generator detects every transient state of the column address strobe signals to form shift pulses that are to be supplied to said shift register, as well as timing signals that are to be supplied to various internal circuits. The dynamic semiconductor memory having such a timing generator operates at high speeds, since it is accessed by the cycle number with a small change of the column address strobe signals.
REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4338679 (1982-07-01), O'Toole
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4397001 (1983-08-01), Takemae
patent: 4405996 (1983-09-01), Stewart
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4472792 (1984-09-01), Shimohigashi et al.
patent: 4567579 (1986-01-01), Patel et al.
patent: 4602353 (1986-07-01), Wawersig et al.
patent: 4707811 (1987-11-01), Takemae et al.
Fujishima et al., "A 256K Dynamic RAM with Page-Nibble Mode", IEEE Journal of Solid State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 470-478.
Gossage Glenn A.
Hecker Stuart N.
Hitachi , Ltd.
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