Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1998-06-05
2000-11-28
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 17, G06F 1750
Patent
active
061548731
ABSTRACT:
A hierarchical layout designing method for an LSI has the step of determining the layout positions and shapes of hard macro blocks and a soft macro block, the step of forming a wiring which connects the hard macro blocks to each other and a path which passes above the soft macro block, the step of evaluating the influence which a wiring passing above the soft macro block will influence on the internal wiring of the soft macro block, a determination step of determining the extending direction in which the cell rows are to extend in the soft macro block, the step of forming in the soft macro block the cell rows in which cells are to be placed, and the step of calculating a first cost "COST x" in the case where the cell rows are formed extending in an x-axial direction and a second cost "COST y" in the case where the cell rows are formed extending in any-axial direction. By the determination step, the first cost "COST x" and the second cost "COST y" are compared with each other, and a direction in which the lower one of the first and second costs is attained is determined as the extending direction of the cell rows.
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Kik Phallaka
Lintz Paul R.
NEC Corporation
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