Method and apparatus for built-in self-test of smart memories

Details Method and apparatus for built-in self-test of smart memories Method and apparatus for built-in self-test of smart memories

1995-06-07

2000-11-28

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714724, 714824, G11C 2900, G01R 3128, G06F 1110

Patent

active

061548618

ABSTRACT:
A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

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