Memory with power supply intercept in redundancy logic

Details Memory with power supply intercept in redundancy logic Memory with power supply intercept in redundancy logic

1990-07-12

1993-08-10

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, 365226, 365227, 371 101, 371 102, 371 103, G11C 700, G11C 2900

Patent

active

052355489

ABSTRACT:
A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.

REFERENCES:
patent: 4367538 (1983-01-01), Shimada
patent: 4417328 (1983-11-01), Ochii
patent: 4587639 (1986-05-01), Aoyama et al.
patent: 4603404 (1986-07-01), Yamauchi et al.
patent: 4635190 (1987-01-01), Meyer et al.
patent: 4639895 (1987-01-01), Iwahashi et al.
patent: 4658379 (1987-04-01), Fujishima et al.
patent: 4733372 (1988-03-01), Nanbu et al.
patent: 4780851 (1988-10-01), Kurakami

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