Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-04-02
2000-11-28
Guay, John
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257408, 257336, 257339, 257343, 257344, H01L 2994
Patent
active
061539163
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an MOS transistor with high output voltage endurance.
2. Description of the Background Art
In a large number of applications, it is desirable that MOS transistors not be destroyed at their output even in case of high output voltages between 180 V and 200 V. It may happen that a circuit is briefly exposed to such high output voltages due to external influences. Such high voltage peaks occur especially in electronic circuits for motor vehicles. That region of an MOS transistor which is most susceptible for a (irreversible) breakdown is the drain-side edge of the gate because rather high electric fields will occur there due to the edge effect. Notably, for reaching a low switch-on resistance, it is desirable that the region between the drain-side edge of the gate and the drain connector itself has a good electric conductivity. This, however, means that the whole output voltage (in the switched-out condition of the transistor) will decrease in the region of the drain-side edge of the gate. Since the gate oxide layer must have a very small thickness, MOS transistors have only a low output voltage endurance unless special measures are taken.
EP-A-0 449 858 describes an NMOS transistor with increased output voltage endurance. In this transistor, the (excessively doped) drain connection area is surrounded by a less doped well of the same conduction type as in the drain connection area. (In case of an NMOS transistor, this conduction type is the n-type conduction.) This less doped n-type well extends to a region below the drain-side edge of the gate oxide layer. The n-type well is produced by ion implantation and subsequent outdiffusion. As a result of the weaker doping as compared to the drain connection area, a doping area with reduced surface concentration in the lateral direction will be generated between the drain connection area and the drain-side edge of the gate oxide layer. In this weaker-doped n-type well area, which is formed in a p-type substrate, a space-charge zone can then be generated to a sufficient extent to make the NMOS transistor resistant to breakdown even in case of higher output voltages. However, the measure described in EP-A-0 449 858 does not allow for any desired increase of the output voltage endurance of the MOS transistor, so that this approach has its limitations.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an MOS transistor which is distinguished by an improved output voltage endurance and, particularly, is resistant to breakdown also in case of output voltages from 160 V to 180 V in the cut-off condition.
To solve the above object, there is proposed in accordance with the invention an MOS transistor comprising type, surface of the substrate, the conduction areas being provided with a heavy, up to excessive, doping and being of a second conduction type opposite to the first conduction type, for drain and source, having a source-side edge adjacent the source connection area and a drain-side edge spaced from the drain connection area, and the substrate from the drain connection area to below the gate oxide layer and spaced from the source connection area, the surface concentration of the doping area in the area adjacent the drain connection area being higher than in the region below the gate oxide layer, outdiffusion of a first partial area adjacent the drain connection area, the size of the first partial area in the drain-gate extension being considerably larger than the penetrating depth of the outdiffusion into the substrate, and of at least one second partial area arranged between the first partial area and the source connection area, the size of the at least one second partial area in the drain-gate extension and the distance thereof to the first partial area being smaller than the penetrating depth of the outdiffusion into the substrate, wherein, while maintaining the same conduction type of the doping area, the individual diffusions originating from the individual, respec
REFERENCES:
patent: 4308549 (1981-12-01), Yeh
patent: 4929991 (1990-05-01), Blanchard
patent: 5132753 (1992-07-01), Chang et al.
patent: 5162883 (1992-11-01), Fujihira
patent: 5646431 (1997-07-01), Hsu et al.
patent: 5650658 (1997-07-01), Beasom
Giebel Thomas
Roth Walter
EL MOS Elektronik in MOS-Technologie GmbH
Guay John
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