Semiconductor memory with pad electrode and bit line under stack

Details Semiconductor memory with pad electrode and bit line under stack Semiconductor memory with pad electrode and bit line under stack

1992-02-07

1993-08-10

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257308, 257756, H01L 2968, H01L 2978, H01L 2992

Patent

active

052351998

ABSTRACT:
A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.
To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.

REFERENCES:
patent: 4748492 (1988-05-01), Iwase et al.
patent: 5012310 (1991-04-01), Kimura et al.
Japanese Journal of Applied Physics, V 18 (1979) Supplement 18-1, pp. 35-42 Koyanagi, Sunami, and Hashimoto.
SIPMOS Technology, an example of VLSI Precision Realized with Standard LSI for Power Transistors, G. Bell/W. Ladenhauf, Jun. 6, 1980, Nr. 4.
Kinney et al., "A Non-Volatile Memory Cell Based on Ferroelectric Storage Capacitors", IEEE, 1987, pp. 850-851.

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