ESD and hot carrier resistant integrated circuit structure

Details ESD and hot carrier resistant integrated circuit structure ESD and hot carrier resistant integrated circuit structure

1995-06-06

1997-05-20

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257327, 257335, 257336, 257337, H01L 2976, H01L 2994

Patent

active

056314850

ABSTRACT:
An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.

REFERENCES:
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5270227 (1993-12-01), Kameyama et al.
patent: 5281557 (1994-01-01), Wu
Hori, Takashi et al., "A New Mosfet with Large-Tilt-Angle Implanted Drain (LATID) Structure," IEEE Electron Device Letters, vol. 9, No. 6, Jun. 1988, pp. 300-302.
Hori, Takashi, "1/4-pm LATID" (LArge-Tilt-angle Implanted Drain)Technology for 3.3-V Operation, IEEE 1989.
Y. Wei et al., "Mosfet Drain Engineering for ESD Performance," EOS/ESD Symposium, pp. 4.3.1-4.3.6., Sep. 16, 1992.
Sabbas Daniel et al., "Process and Design Optimization for Advanced CMOS I/O ESD Protection Devices," EOS/ESD Symposium Proceedings, 1990, pp. 207-213.
D. Duvvury et al. "ESD Phenomena in Graded Junction Devices," Texas Instruments, Inc., pp. 71-76.

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