Flash EEPROM memory cell with polysilicon source/drain

Details Flash EEPROM memory cell with polysilicon source/drain Flash EEPROM memory cell with polysilicon source/drain

1995-09-29

1997-05-20

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257315, 257316, 257321, 438260, 438267, H01L 2976, H01L 29788, H01L 29792

Patent

active

056314825

ABSTRACT:
A method for fabricating an MOSFET device on a lightly doped semiconductor substrate with a first dielectric layer thereon comprises forming a floating gate layer over the first dielectric layer. The floating gate layer is formed into a floating gate line. A doped source region and a doped drain region in the substrate are formed by ion implantation adjacent to the periphery of the floating gate line. The first dielectric layer is etched, exposing the surface of the substrate and the surface of the source region and the drain region aside from the floating gate line. Textured dielectric spacers are formed about the periphery of the floating gate line. Polycrystalline spacers are formed about the periphery of the polysilicon oxide dielectric spacers in electrical contact with the doped regions. The floating gate layer and the dielectric layer and the polysilicon layer are etched to separate the floating gate line into separate floating gates with the spacers separated, forming a blanket interconductor dielectric layer over the device. A blanket deposit of a conductor layer is formed over the interconductor dielectric layer and a control gate mask on the device is used to pattern the conductor layer by etching away portions of the conductor layer unprotected by the control gate mask.

REFERENCES:
patent: 4274012 (1981-06-01), Simko
patent: 4599706 (1986-07-01), Guterman
patent: 5008723 (1991-04-01), van der Have
patent: 5101250 (1992-03-01), Arima et al.
patent: 5108939 (1992-04-01), Manley et al.
patent: 5497018 (1996-03-01), Kajita

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