Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-05-21
1998-06-16
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438656, 438672, H01L 2144
Patent
active
057670153
ABSTRACT:
After an interconnection layer such as Al alloy is formed on an insulating film covering the surface of a substrate, a connection hole is formed through a laminate of the insulating film and the interconnection layer at the area corresponding to the region to be connected. An adhesion layer such as TiN is formed on the interconnection layer, covering the inner surface of the connection hole, and thereafter a conductive layer such as W is formed on the adhesion layer by blanket CVD, burying the inside of the connection hole. The conductive layer is etched back to leave part of the conductive layer in the connection hole as a plug. Through interconnection patterning, an interconnection having a desired pattern is formed which is constituted by the remaining portions of the interconnection layer, the adhesion layer, and the plug. The adhesion layer functions as an antireflection layer during the interconnection patterning. In the interconnection forming method using blanket CVD, the number of processes can be reduced and the reliability of the interconnection can be improved.
REFERENCES:
patent: 4926237 (1990-05-01), Sun et al.
patent: 5106781 (1992-04-01), Penning De Vries
patent: 5326431 (1994-07-01), Kadomura
patent: 5407861 (1995-04-01), Marangon et al.
patent: 5529956 (1996-06-01), Morishita
M. Sato, et al., "Suppression of Microloading Effect by Low-Temperature SiO.sub.2 Etching", Jpn. J. Appln. Phys., vol. 31 (1992), pp. 4370-4375.
Mee Brendan
Niebling John
Yamaha Corporation
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