Method of fabricating self-aligned capacitor

Details Method of fabricating self-aligned capacitor Method of fabricating self-aligned capacitor

1998-10-01

2000-11-28

Fourson, George

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438637, H01L 218242

Patent

active

061535133

ABSTRACT:
A method of fabricating a self-aligned capacitor of a DRAM cell is provided. First, a landing pad and a bit line are formed on a semiconductor substrate. An insulating layer is formed on the landing pad and the bit line. A photoresist layer is formed on the insulating layer and the pattern of the photoresist layer is transferred to the insulating layer. A via hole is formed in the insulating layer using the photoresist layer as a mask to expose the landing pad. Spacers are formed on the sidewalls of the via hole by deposition and self-align etching back. A conductive layer is formed in the via hole. The conductive layer on the insulating layer is removed to form a bottom electrode of a capacitor.

REFERENCES:
patent: 5231044 (1993-07-01), Jun
patent: 5677227 (1997-10-01), Yang et al.
patent: 6027969 (1998-06-01), Huang et al.
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 1, Processing Technology; Lattice Press; p. 428, Aug. 1986.

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