Boots – shoes – and leggings
Patent
1987-05-01
1990-07-10
Williams, Jr., Archie E.
Boots, shoes, and leggings
3642409, 3642426, 3642400, 3642290, G06F 1342
Patent
active
049410830
ABSTRACT:
A processor node providing exclusive read-modify-write operations in a computer system having multiple processors interconnected by a pended bus and employing multiple lock bits. The processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O mode. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the command transfer. The command transfer, including an interlock read command, is stored in an input queue in memory and is processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
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Gillett Jr. Richard B.
Williams Douglas D.
Coleman Eric
Digital Equipment Corporation
Williams Jr. Archie E.
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