Method for producing deep submicron interconnect vias

Details Method for producing deep submicron interconnect vias Method for producing deep submicron interconnect vias

1997-06-10

1999-06-22

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438687, 438640, 438631, 438633, H01L 2144

Patent

active

059152036

ABSTRACT:
A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

REFERENCES:
patent: 5497027 (1996-03-01), Crafts
patent: 5654216 (1997-08-01), Adrian
patent: 5756396 (1998-05-01), Lee et al.
patent: 5801093 (1998-09-01), Lin
Michael T. Welch et al., Pillar Interconnections for VLSI Technology, Jun. 9-10, 1986 V-Mic Conf., pp. 450-456.
S.M. Rossnagel et al., Metal Ion Deposition From Ionized Mangetron Sputtering Discharge, J. Vac. Sci. Technol. B 12(1), Jan./Feb. 1994.
Bruce Roberts et al., Interconnect Metallization for Future Device Generations, Solid State Technology, Feb. 1995.
G.A. Dixit et al., A Robust, Versatile MOCVD TiN Process, Jun. 27-29, 1995 VMIC Conference, 1995 ISMIC--104/95/0175.
Shi-Qing Wang et al., Step Coverage Comparison of Ti/TiN Deposited by Collimated and Uncollimated Physical Vapor Deposition Techniques, J. Vac. Sci. Technol. B 14(3), May/Jun. 1996.
Subhas Bothra et al., W-Plug Via Integration Issues, Solid State Technology, Feb. 1997.

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