Method for manufacturing a CMOS self-aligned strapped interconne

Details Method for manufacturing a CMOS self-aligned strapped interconne Method for manufacturing a CMOS self-aligned strapped interconne

1998-06-04

1999-06-22

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438647, 438655, H01L 214763

Patent

active

059151994

ABSTRACT:
An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

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