Method and apparatus for implementing non-faulting load instruct

Details Method and apparatus for implementing non-faulting load instruct Method and apparatus for implementing non-faulting load instruct

1995-02-27

1998-11-24

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711145, 711203, 711206, 711209, 711165, G06F 1210

Patent

active

058422250

ABSTRACT:
A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page. A second embodiment provides that when the operating system software routine invoked by a TLB miss discovers that a non-faulting load has attempted to access an illegal virtual page that was not previously translated in the translation table, the operating system creates a translation table entry for that virtual page mapping it to a physical page of all zeros and asserting the NFO bit for that virtual page.

REFERENCES:
patent: 4410941 (1983-10-01), Barrow et al.
patent: 5237668 (1993-08-01), Blandy et al.
patent: 5479628 (1995-12-01), Olson et al.
patent: 5530839 (1996-06-01), Kamoto et al.
patent: 5623636 (1997-04-01), Revilla et al.

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