Semiconductor device including a locos type field oxide film and

Details Semiconductor device including a locos type field oxide film and Semiconductor device including a locos type field oxide film and

1991-10-21

1994-04-26

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257370, 257397, 257398, 257514, 257513, H01L 2702, H01L 2704, H01L 2906

Patent

active

053069404

ABSTRACT:
In a semiconductor device having an element isolation region including a LOCOS type field oxide film formed in a surface of a silicon substrate and a U-trench isolation region provided in the silicon substrate, the U-trench isolation region is constituted with a U-trench provided such that it penetrates the field oxide film, a channel stopper provided in a portion of the silicon substrate exposed on a bottom face of the U-trench, a first film in a form of a silicon oxide film formed by thermal oxidation of an exposed portion of the silicon substrate in the U-trench, a second film comprising a buried layer having thermal reflow characteristics and burying the U-trench, a third film having non-thermal reflow characteristics and having a top face substantially coplanar with a top face of the field oxide film and a bottom face connected to a top face of the second films and a fourth film in a form of an insulating film connected to the top face of the third film at an upper end of said U-trench and covering the U-trench. In the element isolation region having this structure, there is no leakage current produced due to thermal oxidation of a polysilicon film buried in the U-trench, contrary to the conventional U-trench isolation region having buried polysilicon film. Further, increase of parasitic capacitance which is caused by thermal oxidation of the buried polysilicon layer can be also restricted.

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C. T. Chuang et al, "On The Scaling Property of Trench Isolation Capacitance for Advanced High-Performance ECL Circuits", 1989 IEEE, IEDM 89-799-802.
M. Sugiyama et al, "Bipolar VLSI Memory Cell Technology Utilizing BPSG-filled Trench Isolation", VLSI Development Division, Bipolar LSI Division, NEC Corporation, pp. 59-60.
Y.-C. Simon Yu et al., "Planarized Deep-Trench Process for Self-Aligned Double Polysilicon Bipolar Device Isolation", J. Electrochem. Soc., vol. 137, No. 6, Jun. 1990, pp. 1942-1950.

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